About

• In this role, you will contribute to the development of System Verilog - UVM test benches, debug test cases, and understand functional coverage models, working closely with senior engineers. Assist in developing and maintaining System Verilog - UVM test benches in collaboration with senior engineers and the team Contribute to creating and enhancing SV UVM verification components, with guidance and supervision from experienced team members Support debugging failing test cases to identify root causes, gaining experience with debugging tools and best practices Assist with defining functional coverage models and ensuring coverage goals are achieved under guidance Participate in team reviews, design discussions, and process improvements, contributing your ideas and learning from team members Help ensure test bench quality and sign-off targets are met, including coverage metrics and functional safety requirements A Bachelor's degree in Electrical/Electronic Engineering or a related field At least 1-2 years of experience in Verification Engineering, with hands-on exposure to System Verilog - UVM (academic, internship, or professional experience) A strong understanding of basic Verification concepts, System Verilog design and testbench fundamentals Eagerness to learn and apply industry-standard verification methodologies like UVM Understanding of debugging workflows and a willingness to learn how to use tools to debug and analyze test issues Strong problem-solving skills, collaborative mindset to work effectively in a team and ability to manage your time effectively Fluency in English (mandatory) We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.