About

• Imagine working in a team where the only limits are the laws of physics and your
• imagination. At Apple, phenomenal ideas have a way of becoming phenomenal
• products and customer experiences very quickly. Bring passion and dedication to
• your job and there's no telling what you could accomplish. The same real passion
• for innovation that goes into our products also applies to our practices. Join
• the team that optimises and delivers world class GPUs into Apple Silicon. As
• part of the GPU FE Implementation team, you’ll be responsible for crafting and
• building a GPU that enriches the lives of millions of people every day. Join us!

• DESCRIPTION

• Candidates will be responsible for PPA optimisation of the netlist, working
• collaboratively with the RTL and Physical design teams. You will also deliver
• key netlist quality milestones for your partition and be involved in
• understanding and improving our current methodologies. Through this
• collaboration, you will deliver the outstanding GPU’s for the best consumer
• products. If you’re ready to help chart the future of Apple Silicon, we would
• love to talk to you.

• MINIMUM QUALIFICATIONS

• Familiarity with DFT insertion; Familiarity with reset domain, multi-clock
• domain, multi-power domain (UPF), linting tools and concepts across RTL and
• Gate-Level; Experience implementing ECO's for functionality and timing.
• Experience with physical synthesis, including logic and PPA optimisation
• techniques. Ability to analyze critical paths and guide RTL designs to efficient
• solutions. Experience using logic equivalence tools for RTL and Gate-level
• designs. Collaborate optimally with IP teams spanning multiple sites.